The present invention relates generally to electronic circuits, and more particularly to comparator circuits which can support two or more inputs.
Conventional comparators generally determine which of two inputs is the greater or the lesser of the two. An example of such a comparator is a sense amplifier typically used in applications such as dynamic random access memory (DRAM) cells. FIG. 1 illustrates the operation of a conventional sense amplifier 10. The amplifier 10 receives two inputs, x1 and x2, and generates two outputs, d1 and d2. If the value of input x1 is greater than that of input x2, the output d1 is at a logic high level, i.e., d1=1, and the output d2 is at a logic low level, i.e., d2=0. Alternatively, if the value of input x1 is less than that of input x2, the output d1=0, and the output d2=1. The values of the outputs d1 and d2 thus indicates the relative values of the inputs. Additional details regarding the operation of a conventional sense amplifier can be found in, for example, S. Aur et al., xe2x80x9cIdentification of DRAM Sense-Amplifier Imbalance Using Hot Carrier Evaluation,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. 27, No. 3, pp. 451-453, March 1992.
Unfortunately, using conventional comparators to determine, for example, which of three inputs is greater or lesser than the others, generally results in circuit arrangements which exhibit excessive computation time and signal delay, require a large amount of circuit area, and consume a large amount of power. Other problems associated with conventional multi-input comparators include, for example, an inability to determine a maximum or minimum input value from among any given set of N inputs, and an inability to arrange the inputs in an ascending or descending order.
As is apparent from the above, further improvements are needed in order to provide multi input comparators which are more computationally efficient, exhibit less signal delay, require less circuit area, and consume less power. Moreover, a need exists for a multi-input comparator which can identify the maximum or minimum value from among a set of inputs, or arrange the inputs in an ascending or descending order.
A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of input signal values. The multi-input comparator includes a series combination of a first comparison circuit, such as a sense amplifier, and a first multiplexer. A subset of the set of input signal values is applied to inputs of the first sense amplifier. The first multiplexer also receives as its inputs the signal values applied to the first comparison circuit, and a select signal input of the first multiplexer is driven by an output of the first comparison circuit. The output of the first multiplexer is used as an input for one or more additional groups of circuitry, each including series combination of a comparison circuit and a corresponding multiplexer. These additional groups of circuitry may be arranged in a linear architecture, a logarithmic architecture or combinations of these architectures. Accordingly, depending on the particular combination of the additional groups, the comparator may be configured with any desired number N of inputs. The output of one of the multiplexers in one of the additional groups of circuitry corresponds to either the maximum or minimum value of the set of input signal values. Including the first comparison circuit and multiplexer, a comparator for processing a set of N signal values has a total of N-1 groups of circuitry, each including a comparison circuit and a multiplexer.
In accordance with another aspect of the invention, the multi-input comparator may be used in conjunction with a position determination circuit which indicates the position of the maximum or minimum value in the set of signal values. Advantageously, the information generated by the position determination circuit may also be used to produce a desired ordering of the input signal values, such as a list of the signal values in ascending or descending order of signal value magnitude.
A multi-input comparator in accordance with the invention can provide substantial improvements in computation time, signal delay, required circuit area and power consumption. In addition, a multi-input comparator in accordance with the invention may be utilized with a variety of different types of comparison circuits, including sense amplifiers having two inputs or sense amplifiers having more than two inputs. These and other features and advantages of the present invention will become more apparent from the accompanying drawings and the following detailed description.